The present invention relates to a nonvolatile semiconductor memory and a method for manufacturing the same and, more specifically, to a flash EEPROM (Electrically Erasable Programmable Read-Only Memory) capable of erasing and writing data together by electrical signals.
Recently a demand for increasing the speed and capacity (degree of integration) of a semiconductor memory has become stronger and stronger, as has a demand for miniaturizing the devices. These demands are true of a nonvolatile semiconductor memory such as an EPROM (Erasable PROM) and an EEPROM using a two-layered gate of a stacked structure.
Miniaturization of memory cells is essential to an increase in capacity of a semiconductor memory. As one method for achieving this, the SAC (Self-Align Contact) technique has conventionally been known and, using this technique, a contact hole is decreased in diameter.
FIGS. 1A and 1B illustrate a process of manufacturing a prior art nonvolatile semiconductor memory in which a contact hole can be formed finely using the SAC technique or a PEP (Photo Engraving Process) of a contact. For example, in a memory cell transistor region, an element isolating field oxide film (not shown) is formed on a P-type semiconductor substrate 301, and then a gate insulation film 302, a floating gate electrode 303, an ONO (oxide/nitride/oxide) film 304, a control gate electrode 305, and an SiN film 306 serving as a cap material are sequentially stacked one on another thereby to form a two-layered gate section. Then, ions are implanted to form both a source diffusion layer 307a serving as a source region and a drain diffusion layer 307b serving as a drain region on the surface of the substrate 301. After that, an SiN film 308 is formed on the entire surface of the resultant structure, and an interlayer insulation film 309 is deposited on the entire surface of the SiN film 308. The surface of the insulation film 309 is flattened by the CMP (Chemical Mechanical Polishing) technique. In order to reduce the amount of polishing, that portion of the interlayer insulation film 309, which is separated at a distance (margin D) from the upper surface of the SiN film 308 on the two-layered gate section, is flattened.
After that, a contact is formed through the PEP using the SAC technique and, in other words, a resist pattern 310 is formed on the interlayer insulation film 309. In accordance with the resist pattern 310, the interlayer insulation film 309 is etched by anisotropic etching such as RIE (Reactive Ion Etching) in self-alignment with the SiN film 308. Thus, contact holes 311 are formed selectively in the interlayer insulation film 309. These holes are finely formed at the same interval as that between the two-layered gate sections.
However, an opening type pattern having an opening portion 310a formed in which position the contact holes 311 are made, is generally used as the resist pattern 310 for the PEP of contacts. The margin of the PEP is therefore reduced in accordance with miniaturization of the contact holes 311. The thickness (H) of a portion of the interlayer insulation film 309, which is removed by RIE, is equal to the total of the height of the two-layered gate section and the margin (D) thereabove, as shown in FIG. 2. The ratio of the depth of each of the contact holes 311 (thickness H of the interlayer insulation film 309) to the width (A) thereof, or a so-called aspect ratio (H/A) is increased too much.
As the miniaturization of contacts is promoted, it becomes more difficult to sufficiently make the contact holes 311, keeping the selective ratio of the interlayer insulation film 309 to the SiN film 308 high. Consequently, the problems that no contact hole is formed and a short circuit is caused between the gate and contact, are easy to arise.